A via, a plated hole etched in one or more layers of an integrated circuit and used to provide a vertical connection between different layers, may be used for many different purposes. A via may provide electrical connectivity between different layers of the integrated circuit. Additionally, in a micro-electro-mechanical system (MEMS) a via may provide mechanical connectivity between structures in the integrated circuit. A via may also be used to provide both electrical and mechanical connectivity.
In a digital micromirror device (DMD) based projection display system, wherein a large number of micromirrors pivot along an axis based on image data from an image being displayed, a via may be used to provide electrical connectivity between distant conductive layers and conductors. Additionally, a via may be used to create a support member for each micromirror, physically attaching the micromirror to a hinge.
An electrically conductive via may be created by first etching a hole in at least one layer of an integrated circuit and then coating the walls of the hole with a metallic material, such as aluminum, tungsten, copper, and so forth, or another conductive material, such as polysilicon, using a directional (anisotropic) deposition technique, such as evaporation or sputtering, or a non-directional (isotropic) deposition technique, such as chemical vapor deposition. The directional and non-directional deposition techniques may produce vias that are adequate for use in providing electrical connectivity. Non-electrically conductive vias may also be created using the same techniques and materials, however, these techniques may not provide adequate mechanical strength to provide long-term reliability.
A technique used to help strengthen the via as well as increase its electrical and mechanical conductivity is to taper the walls of the via, such as disclosed in U.S. Pat. No. 5,269,880, entitled “Tapering Sidewalls of Via Holes,” which is incorporated herein by reference. The tapered via walls permit better step coverage using the directional and non-directional deposition techniques. A disadvantage of the disclosed technique is the requirement of additional process steps to protect the bottom of the opening with a protective layer prior to the sputtering or etching, and then removing the protective layer after the sputtering or etching.
Another technique used to help strengthen the via involves the use of a spacer within the via. The spacer does not require the use of a protective layer that will need to be subsequently removed, thereby reducing the complexity of the manufacturing of the integrated circuit. U.S. Pat. No. 4,489,481, entitled “Insulator and Metallization Method for VLSI Devices with Anisotropically-Etched Contact Holes,” which is incorporated herein by reference, discloses an example of such a technique with spacers created from an oxide material. U.S. Pat. No. 6,171,964, entitled “Method for Forming a Conductive Spacer in a Via,” which is incorporated herein by reference, discloses an example of such a technique with spacers formed using metallic materials.